SoC Design Engineer

Oversees definition design verification and documentation for SoC (System on a Chip) development. Determines architecture design logic design and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries functional units and sub-systems into SoC full chip designs Register Transfer Level coding and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis place and route timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure conducts experimental tests and evaluates results. May also review vendor capability to support development. Job Purpose

We are seeking an experienced RTL Design Engineer to drive the architecture design implementation and optimization of complex digital logic for next-generation NAND Flash memorybased SSD controllers . This role involves translating system-level requirements into efficient microarchitecture and synthesizable RTL driving design tradeoffs across performance power and area (PPA) and delivering high-quality designs through ASIC implementation and silicon validation.

You will work at the intersection of digital design computer architecture NAND Flash technology and storage systems partnering with architecture firmware verification physical design and silicon validation teams to develop scalable and reliable controller solutions for advanced SSD products.

Key Responsibilities

• RTL Design and Microarchitecture- Architect design and implement complex RTL modules using Verilog/SystemVerilog for NAND Flash memorybased SSD system and microarchitecture specifications into efficient synthesizable reusable and maintainable microarchitecture tradeoffs involving throughput latency buffering concurrency resource utilization and and optimize controller pipelines state machines arbitration logic queues FIFOs DMA engines and memory interfaces.
• NAND Flash Controller Design- Develop and optimize hardware logic for NAND command sequencing interface control data transfer status handling error recovery and timing management. Understand NAND Flash read program and erase behavior including device timing constraints operating modes error conditions and technology-specific requirements. Design controller logic that supports high channel utilization parallel NAND operations efficient resource scheduling and robust error handling. Collaborate with firmware and architecture teams on hardware/software partitioning and optimization of controller functionality.
• Performance Power and Area Optimization- Analyze and optimize RTL to meet stringent timing throughput latency power and silicon-area targets. Identify critical timing paths pipeline bottlenecks resource conflicts and inefficient logic structures. Drive design improvements through architectural changes logic restructuring pipelining resource sharing and power-aware design techniques. Evaluate synthesis and static timing analysis reports and work with physical design teams to resolve timing and implementation challenges.
• ASIC Design and Integration- Own RTL development through synthesis readiness subsystem integration and ASIC implementation handoff. Ensure design quality through lint clock-domain crossing (CDC) reset-domain crossing (RDC) and design-rule checks as applicable. Address clocking reset initialization parameterization and low-power requirements. Collaborate with design verification teams to define verification strategies resolve functional issues and achieve robust design coverage. Support pre-silicon emulation silicon bring-up post-silicon debug and root-cause analysis of hardware issues.
• Data Integrity and Reliability- Integrate or develop interfaces to ECC/LDPC engines data-protection logic and other reliability-related controller subsystems. Implement robust error detection status reporting recovery sequencing and fault-handling mechanisms. Collaborate with reliability and firmware teams to address NAND error behavior data integrity and system-level fault scenarios.
• Technical Leadership and Collaboration- Drive design reviews provide technical guidance to team members and promote RTL coding and design best practices. Work closely with firmware architecture verification physical design NAND technology and validation teams to resolve cross-functional issues. Identify design risks early evaluate alternative implementations and drive issues to closure. Contribute to design methodologies automation technical documentation and continuous improvements in ASIC development efficiency.

Qualifications :

Required Qualifications

• Masters or PhD degree in Electrical Engineering Computer Engineering Computer Science or a related field .
• Typically 3 years of relevant experience in RTL design and ASIC development.
• Strong proficiency in Verilog/SystemVerilog and experience designing complex synthesizable RTL.
• Deep understanding of digital logic sequential design finite-state machines pipelining timing closure and computer architecture.
• Experience with ASIC design flows including RTL simulation lint synthesis static timing analysis (STA) and design integration.
• Experience analyzing timing reports and optimizing RTL to meet performance power and area requirements.
• Strong understanding of clocking reset architecture CDC and robust hardware design practices.
• Proficiency in scripting or programming using Python Tcl Perl or C/C to automate design tasks and analyze results.
• Demonstrated ability to debug complex hardware issues perform root-cause analysis and collaborate effectively across engineering teams.

Preferred Qualifications

• Experience designing NAND Flash memory controllers SSD controllers or other high-performance storage ASICs .
• Strong understanding of SSD architecture Flash Translation Layer (FTL) interactions NAND parallelism and storage data paths.
• Experience with NAND interfaces and protocols including ONFI or Toggle-mode interfaces and associated timing and command requirements.
• Knowledge of NAND Flash reliability characteristics error management ECC/LDPC bad-block handling and read-retry mechanisms.
• Experience designing high-throughput data paths DMA engines queue management arbitration buffering and memory interfaces.
• Familiarity with industry-standard EDA tools for simulation synthesis lint CDC/RDC and static timing analysis.
• Experience with low-power design techniques clock gating power management and PPA optimization.
• Experience with formal verification hardware emulation FPGA prototyping or post-silicon debug.
• Understanding of interface protocols such as AXI AHB PCIe or NVMe-related controller interfaces.
• Experience with design automation RTL quality analysis or AI-assisted hardware design and verification workflows.
• A track record of technical ownership cross-functional problem-solving and delivery of complex ASIC designs from specification through silicon validation.

Additional Information :

This position is also eligible to participate in Solidigms restricted stock unit (RSU) restricted cash unit (RCU) and cash bonus addition Solidigm offers a benefits package that includes medical dental vision supplemental life and AD&D insurance; short- and long-term disability; healthcare and dependent care flexible spending accounts and a company match on eligible 401(k) plan contributions.

The compensation range for this role is $167360 - $267800. Actual compensation is influenced by a variety of factors including but not limited to skills experience qualifications and geographic location.

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Remote Work :

No

Employment Type :

Full-time