Memory Subsystem Architect & P&R Engineer
Broadcom
Broadcom seeks an energetic design engineer to join the Central Engineering Group and drive memory subsystem design. The role focuses on architecture, RTL implementation, and physical design for large memory blocks in a fast-paced environment. Minimum 8 years in the field and a B.S. in Electrical Engineering are required. Strong Verilog, Python scripting, and proficiency with STA/DRC/EM/IR tools are essential for design closure and project success. #J-18808-Ljbffr Broadcom
Vacancy posted 3 days ago
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