Memory Subsystem Architect & Physical Design Lead
Broadcom Inc.
Broadcom Inc. is seeking an experienced design engineer to join the Central Engineering Group for memory subsystem development. You will design memory blocks, implement RTL, and drive timing and physical design closure. The role requires strong Verilog, RTL, place-and-route, and scripting skills, with leadership and collaboration across teams. Eligible for bonus and equity awards as part of compensation. #J-18808-Ljbffr Broadcom Inc.
Vacancy posted 4 days ago
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