Senior Chip Lead - Physical Design Architect
Cadence Design Systems, Inc.
Cadence Design Systems, Inc. in Austin seeks highly skilled Physical Design Architects and Chip Leads to drive RTL-to-GDS services for advanced FinFETs. You will lead a design team, own critical decisions, and work with customers to meet PPAS targets. Key responsibilities include directing design for test, sign‑off criteria, and toolchain optimization, with collaboration across Cadence and client teams. This role requires extensive experience, high-level problem solving, and strong scripting #J-18808-Ljbffr Cadence Design Systems, Inc.
Vacancy posted 2 days ago
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