Design Verification Engineer, Digital Signal Processing

Design Verification Engineer, Digital Signal Processing Google – Sunnyvale, CA, USA Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field. 8 years of experience in design verification (DV) with a focus on digital signal processing (DSP), communication systems, or arithmetic logic blocks. Experience with scripting in Python, Perl, or Makefile for automation. Preferred qualifications Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field. Experience with Bit‑Exact Verification comparing RTL against MATLAB or C++ golden models. Experience with assertion‑based verification (SVA) and functional coverage closure. Familiarity with high‑speed protocols such as Ethernet (802.3) or PCIe. Knowledge of fixed‑point arithmetic and quantization error analysis. About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google’s most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a Design Verification Engineer, you are the gatekeeper of functional integrity. You will build the environments that prove our high‑speed DSP blocks (Filters, AGCs, and Equalizers) are bit‑exact to our architectural models, ensuring no mathematical bugs reach the tape‑out stage. Responsibilities Design, build, and maintain constrained‑random verification environments using SystemVerilog and UVM for individual DSP blocks (e.g., AGC, FFE, DFE, and Interpolators). Develop golden model checkers to compare RTL output against architectural models (MATLAB/C++/SystemC) to ensure accuracy. Define and implement functional coverage plans, using covergroups and assertions (SVA) to ensure all architectural corner cases and fixed‑point overflows are exercised. Create complex sequences and virtual sequencers to stress‑test DSP adaptation loops under various noise and jitter profiles. Lead the debugging of RTL failures, working closely with DSP designers to resolve discrepancies between the hardware implementation and the algorithmic specification. Compensation and Benefits US base salary range for this full‑time position is $163,000–$237,000 plus bonus, equity, and benefits. Compensation is determined by role, level, and location. Additional benefits include health, dental, vision, and other standard Google benefits. Equal Opportunity & EEO Statement Google is an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity or expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy, or related conditions (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. #J-18808-Ljbffr Google Inc.