Principal Digital Verification Engineer

Principal Digital Verification Engineer Job Description Verification of DDR5 Data Buffer to meet functional and performance specifications. Be able to integrate and test on System-level and block level using UVM methodology. Participate in feasibility studies. Support in developing verification plan based on specifications. Support in Verification planning, maintenance, feature extraction, verification tests, coverage and checker development. Develop efficient, reusable state‑of‑the‑art verification environments and testbench structures. Optimize solutions for key indicators such as reusability, performance and ease of use. Identify and communicate improvements that may ease verification and/or improve design behavior. Support in optimizing UVM based testbench. Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. Key Responsibilities Drive the Memory interface products verification effort, including defining the verification strategy, developing test plans, coverage, and executing tests. Technically work with a team of verification engineers, providing technical guidance and mentoring as needed. Drive and quality control the creation of a verification test plan. Work closely with the design team to ensure that the design meets the requirements and is testable. Identify and drive improvements to the verification process to ensure the highest levels of quality and efficiency. Drive and monitor coverage of design verification. Provide regular updates to management on the status of the verification effort. Qualifications Masters in Electrical Engineering, Computer Engineering, or equivalent with 8+ years of experience. Bachelor's Degree in Electrical Engineering, Computer Engineering, or equivalent with 10+ years of experience. Company Description Renesas is looking for a talented individual for their memory interface products. These memory interface products mainly go to datacenters for AI and cloud computing, providing the highest bandwidth for intensive computing while consuming low power. This exciting role is responsible for the development of digital sections of leading‑edge memory data buffer chips for DDR5, DDR6 and beyond. #J-18808-Ljbffr Renesas