Senior Power Delivery & Integrity Engineer

We are seeking a highly skilled Senior Power Engineer to take a leadership role in defining the board‑level and rack‑level power delivery architecture for our next‑generation, multi‑kilowatt AI server platforms. This critical position owns the end‑to‑end design of high‑current power delivery paths to advanced SoCs, encompassing the definition of voltage conversion and regulator strategy, comprehensive Power Delivery Network design including efficient decoupling schemes, and driving critical design tradeoffs to maximize efficiency, optimize thermal performance, and ensure overall system performance, all while considering compatibility with OCP/Open Rack power distribution standards. You will work cross‑functionally with silicon, mechanical, thermal, and systems engineers to deliver robust, efficient, and scalable power delivery for these complex platforms. Responsibilities Architect and design board‑level, server‑level, and rack‑level power delivery systems for high‑power subsystems. Define PDN topology, including VRMs, POLs, vertical and lateral power routing, and high‑current interfaces. Perform component selection (VRMs, FETs, inductors, bulk caps, MLCCs, connectors, busbars) and create derating, margin, and reliability guidelines. Lead decoupling capacitor strategy across package and PCB layers to meet target impedance and transient response goals. Drive power integrity analysis (AC/DC, Z‑target, transient, EMI/EMC) and validate designs through modeling, simulation, and lab measurement. Collaborate with mechanical and thermal teams to ensure high‑current routing, cooling requirements, and system constraints are aligned. Partner with silicon and package engineering to co‑design vertical PDN paths, including socket interfaces, pin/bump maps, and transient load profiles. Review and advise silicon design to improve power integrity. Develop test plans for PDN validation, transient load tests, impedance measurement, and system bring‑up. Provide expertise during failure analysis, root‑cause investigations, and corrective actions for system power issues. Qualifications BS/MS in Electrical Engineering or related field. 10+ years of experience in high‑power delivery design. Demonstrated experience designing high‑current, low‑voltage power delivery for SoCs. Deep expertise in power integrity, PDN modeling, VRM design, target impedance definition, and transient response optimization. Proficiency with SPICE, PDN simulation tools (Keysight, Cadence Sigrity/Clarity, Ansys SIwave), and measurement equipment (VNAs, oscilloscopes, electronic loads). Solid understanding of package‑to‑PCB PDN interactions. Strong communication and cross‑functional collaboration skills. Preferred Familiarity with EMI/EMC mitigation in high‑current environments. Experience in server‑class PCB design, including stackup planning, high‑current routing, and decoupling strategies. Background in thermal‑mechanical co‑design for high‑power modules. Knowledge of rack‑level power architectures, ORv3/OCP standards, power shelves, and busbar systems. #J-18808-Ljbffr Majestic Labs ai