Senior DFx Methodology Architect (San Jose)

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Our global team is growing, and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. THE PERSON: This position invites candidates to join a small team of experts, inventing and implementing original solutions, addressing challenging DFx problems in some of the industry’s largest and most complex SOCs. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Define constraints and dependencies for IPs based on block interfaces, power supply & configuration requirementsAddress and improve efficiency of timing, PnR, DRC and integration methodologies for DFx IPsDevelop new IPs and methodologies, including process characterization IP (timing, defectivity etc.) for test-vehiclesDefine DFx Architecture for AMD’s next generation monolithic and stacked SoC product families, including testability, debug, characterization, repair and yieldWork with functional IP teams on integration, analysis and qualification methodologies for a growing number of DFx IPs, tools and flowsPREFERRED EXPERIENCE: RTL design, timing constraints and design methodologiesDesign qualification –STA, RTL-DRC, CDC, RDC, Constraints checkingProgramming experience – Perl, TCL, PythonDesign verification – Verilog simulation, coverage analysis, assertionsPrior knowledge of Scan design, ATPG, Memory BIST, Repair and harvesting for yield are a plusACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering This role is not eligible for visa sponsorship.#LI-CJ3#LI-HybridBenefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.