Physical Verification Engineer

Job Details:Job Description: About Intel Foundry ServicesIntel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.Position OverviewThe Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape-outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.Key ResponsibilitiesPhysical Verification Support & Issue ResolutionProvide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challengesCollaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolutionResolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementationsTechnical Content Development & TrainingCreate application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teamsDrive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outsDevelop best practice guidelines for physical verification flows and methodologies across advanced process technologiesVerification Methodology LeadershipLead optimization of physical verification flows for advanced CMOS processes (22nm and below)Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementationsDrive methodology improvements to streamline customer design workflows and enhance verification productivityCustomer Engagement & Technical ExcellenceDeliver customer-facing technical support with focus on physical verification challenges and solutionsSupport customers through complex verification issues and advanced process technology adoptionEnsure maximum customer satisfaction through expert guidance and responsive technical supportCore CompetenciesSelf-driven and results-oriented with capability to effectively manage multiple complex tasksStrong analytical problem-solving skills for complex physical verification challengesEffective communication skills with experience in collaboration, active listening, and providing constructive feedbackQualifications:The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum QualificationsUS Citizenship requiredAbility to obtain a US Government Security ClearanceBachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study3+ years of experience with advanced CMOS processes (22nm and below)3+ years of combined experience in layout verification and parasitic extraction EDA tools3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting.)Preferred QualificationsActive US Government Security Clearance with a minimum of Secret levelPost Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of studyHands-on experience in one or more areas ( LVS, DRC,ERC, PERC)Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA toolsExperience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA toolsRule deck coding experience in ICV, Calibre or Pegasus EDA toolsExperience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design workCustomer facing experienceWhat We OfferOpportunity to work with cutting-edge physical verification technologies for aerospace, defense, and government applicationsDirect customer engagement and technical leadership in advanced semiconductor verificationAccess to Intel's most advanced foundry technologies and comprehensive verification tool suitesCompetitive compensationProfessional development in physical verification methodologies and foundry servicesDirect impact on national security through advanced semiconductor verification solutionsJob Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, Arizona, Phoenix; US, California, Santa Clara; US, Oregon, HillsboroType: Full time