Manager, ASIC Design Engineering (Starshield Silicon)

Manager, ASIC Design Engineering (Starshield) Lead a team that develops ASICs and FPGAs for cutting‑edge satellite systems, guiding design from concept through on‑orbit operations to enhance national security capabilities. Responsibilities Lead a small team responsible for the digital design of ASICs and/or FPGAs for Starshield projects. Lead architectural trade‑offs for features, performance requirements, and system limitations; derive specifications and coordinate with modem/DSP and RFIC engineers to partition functions between hardware and software. Define micro‑architecture, implement RTL in Verilog/SystemVerilog, integrate into top level, and deliver a fully verified, synthesis/timing‑clean design. Collaborate with the verification team to ensure comprehensive coverage and verification of all design aspects. Work with engineering leadership to drive product requirements and push performance envelopes for Starshield satellites. Recruit, develop, train, and retain a world‑class engineering team. Provide timing constraints for IPs and support the physical implementation team (synthesis, timing closure, formality checks). Participate in silicon bring‑up and validation; assist in developing automated test lab equipment for laboratory measurements. Basic Qualifications Bachelor’s degree in electrical engineering, computer engineering, computer science, or a related engineering discipline. 5+ years of experience in RTL implementation and/or FPGA/ASIC development. 2+ years of experience managing or mentoring an engineering team. Preferred Skills and Experience Experience solving clock domain crossings and power optimization challenges. Experience developing complex ASICs. Experience with multicore CPU subsystem design. Experience with standard bus protocols (e.g., AXI, AHB). Experience with embedded processors. Knowledge of high‑speed and low‑power design techniques. Proficiency in scripting languages (Python, TCL, etc.). Familiarity with EDA tools such as HDL simulators (VCS, Questa, IES), HDL lint tools (Spyglass), and FPGA tools (Xilinx Vivado, Altera Quartus II). Ability to work in a dynamic environment with evolving needs. Team‑player with a can‑do attitude who performs well individually and collaboratively. Enjoyment of challenge and continuous learning. Additional Requirements Willingness to work long hours and weekends as needed to meet critical milestones. Willingness to travel for off‑site testing. Active TS‑SCI clearance is preferred; clearances may qualify for a 10% salary differential (up to $20,000). Compensation and Benefits Manager: $190,000.00 - $245,000.00 per year. Base salary is determined by experience, education, and knowledge. Eligible employees with an active clearance receive a 10% differential, up to an additional $20,000 annually. Benefits include long‑term incentives (company stock or cash awards), discretionary bonuses, an Employee Stock Purchase Plan, comprehensive medical, vision, and dental coverage, a 401(k) retirement plan, short‑ and long‑term disability insurance, life insurance, paid parental leave, 3 weeks of paid vacation, 10+ paid holidays, and paid sick leave in accordance with company policy and law. ITAR Requirements Applicants must be a U.S. citizen or national, U.S. lawful permanent resident, refugee, asylee, or eligible to obtain the necessary authorizations from the U.S. Department of State. Equal Opportunity Employer The company is an Equal Opportunity Employer; employment is based on merit, competence, and qualifications and will not be influenced by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, or any other legally protected status. #J-18808-Ljbffr United States Digital Space LLC