Design Director

POSITION OVERVIEW The Design Director leads the Dallas Design Center's analog/mixed-signal IC design organization responsible for New Product Introduction (NPI) in the Power Path category - eFuse, Load Switch, and Ideal Diode product families - within one of our Power product lines. The role carries full responsibility for design, verification, and layout engineering execution from product concept through Release-for-Supply, and reports directly to the General Manager, Power product line. This is a player-coach leadership position: the Design Director combines deep hands‑on analog/power IC design expertise with proven design management capability to deliver first-pass silicon success, develop engineering talent, and build the design capability that underpins the Power Path growth strategy. KEY RESPONSIBILITIES Lead and manage a multi‑disciplinary team of analog/mixed‑signal design, digital design, verification, and layout/mask design engineers executing concurrent NPI projects from concept through volume production release Own technical oversight of all design phases: product architecture, transistor‑level circuit design, simulation and verification, physical layout, tape‑out, silicon bring‑up/validation, and characterization support through all MRA gates to RFS Drive first‑pass silicon success through rigorous design review discipline, design‑for‑quality practices (ESD, latch‑up, EM/IR, DFT, DFM), and disciplined MRA gate readiness Contribute to product definition in partnership with Systems Engineering and Product Management: assess feasibility, negotiate IC development trade‑offs (cost, performance, schedule, die size), and translate end‑system requirements into executable design specifications Drive the shared IP core strategy across the Power Path portfolio (power FET integration, charge‑pump gate drive, current‑limit loops, ideal‑diode control, protection circuits), maximizing design reuse and time‑to‑market across eFuse, Load Switch, and Ideal Diode families Plan and allocate design resources across concurrent NPIs; own design capacity planning, EDA/CAD tooling needs, and critical‑competency coverage for the Dallas Design Center Recruit, develop, mentor, and retain top design engineering talent; conduct performance management, build succession depth, and eliminate sole‑expert risk in critical design competencies Collaborate across global design sites (Nijmegen, Delft, Hamburg, Osaka) and cross‑functional partners (Product Engineering, Test Engineering, Package Engineering, Quality, PMO) to ensure aligned, on‑schedule NPI execution Support key customer engagements: design‑in support for strategic accounts, technical escalation resolution, and credible customer‑facing representation of design capability and product performance Maintain competitive awareness of benchmark products and design approaches (TI, ADI, MPS, Rohm, Infineon, ST) and apply insights to product definition and design differentiation Provide sustaining design support for released products: failure analysis, yield enhancement, and design‑related quality issue resolution Act as site design leadership for the Dallas Design Center, partnering with HR, Facilities, and corporate functions to maintain an effective, engaged design organization SKILLS / COMPETENCIES Hard Skills Minimum Bachelor's Degree in Electrical Engineering; MSEE/PhD preferred, with focus on analog and/or power IC circuit design 10+ years of hands‑on analog/mixed‑signal power IC design experience, including transistor‑level circuit design, physical layout oversight, and silicon validation in BCD/BiCMOS/CMOS process technologies (12V‑150V class) Demonstrated design management experience leading teams of 10+ engineers across design, verification, and layout disciplines, with a sustained track record of released products in volume production Direct design experience in power‑path protection and distribution products - eFuses, load switches, ideal diode controllers, hot‑swap controllers, surge stoppers - or closely adjacent power management ICs (DC‑DC converters/controllers, gate drivers, PMICs) Deep command of power management design fundamentals: integrated power FETs, charge pumps, current‑sense and current‑limit architectures, protection circuits (OVP/UVLO/OCP/TSD), precision references, comparators, and low‑IQ design techniques Mastery of modern analog design flows and verification methodologies (Cadence environment, SPICE‑class simulation, LVS/DRC, reliability sign‑off: ESD, latch‑up, EM/IR) Track record of first‑pass silicon success and datasheet‑quality documentation ownership; patents and publications a plus Soft Skills Proven people leadership: hiring, mentoring, performance management, and team development Succinct executive communication that captures risk, status, and progress accurately Excellent analytical skills and structured, disciplined work approach Entrepreneurial ownership mentality; drives lowest‑risk path that achieves project #J-18808-Ljbffr