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Silicon Design Package Engineer

AceStack LLC

Role: Silicon Design Package Engineer
Location: Santa Clara, CA

This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies


Tools & Knowledge:


Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).


Technical Expertise:


Multi-layer package design experience.


Understanding of substrate manufacturing Design Rules and Assembly Rules .


Familiarity with SIPI (Signal Integrity & Power Integrity) Rules .


Flip-chip package design concepts
Vacancy posted 5 hours ago
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