Senior ASIC Digital Architect | DDR/PCIe/UCIe Protocols
Synopsys Inc
Synopsys Inc is seeking an experienced ASIC Digital Architect to define and drive RTL design and verification at both chip and block levels. You will create design plans for DDR, PCIe, CXL, UAL, and UCIe IO protocols and work with cross-functional teams to ensure seamless integration and high-quality results. You will mentor junior engineers, promote best practices, and guide the architectural direction while communicating with stakeholders to align on goals and deliverables in a fast-paced #J-18808-Ljbffr Synopsys Inc
Vacancy posted 2 days ago
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