ASIC & FPGA Design Engineer

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior ASIC & FPGA Design Engineer based in the United States. Join a technically advanced engineering environment where you will design and develop high-performance digital and mixed-signal integrated circuits and FPGA solutions. As a Senior ASIC & FPGA Design Engineer, you will contribute to the full hardware development lifecycle, from architecture and RTL design to verification, implementation, and system integration. You will leverage your expertise in VHDL, Verilog, and SystemVerilog to build reliable, efficient designs that meet demanding performance and timing requirements. Working closely with architecture, systems, firmware, and product engineering teams, you will help solve complex implementation challenges and deliver robust hardware solutions. Your responsibilities will include verification strategy, timing analysis, design optimization, and support for laboratory integration and troubleshooting. This fully remote contract opportunity offers the chance to apply advanced digital design expertise to technically challenging projects alongside multidisciplinary engineering teams. The initial contract runs from October 12, 2026, through June 30, 2027, with potential full-time conversion subject to business needs and relocation requirements. Accountabilities As a Senior ASIC & FPGA Design Engineer, you will lead and contribute to the design, verification, implementation, and integration of advanced hardware solutions. You will work across the engineering lifecycle to ensure designs meet functional, performance, quality, and reliability requirements. - ASIC and FPGA design: Design, develop, and implement digital ASICs, FPGAs, and potentially mixed-signal ASICs using hardware description languages such as VHDL, Verilog, and SystemVerilog.

- RTL development and implementation: Translate design specifications and architectural requirements into efficient, synthesizable RTL, addressing performance, resource utilization, and implementation constraints. - Verification methodology: Develop verification strategies, test benches, and test harnesses for block-level and system-level designs to ensure functional correctness and design reliability. - Test planning and coverage: Create and execute comprehensive test plans, implement coverage models, and establish verification processes that identify design issues early in the development cycle. - Timing and design signoff: Conduct timing analysis, noise analysis, and other signoff checks to validate design integrity and compliance with technical specifications. - Design optimization and troubleshooting: Identify and resolve implementation challenges involving timing closure, congestion, and other hardware design constraints, driving issues through to resolution. - Cross-functional collaboration: Work closely with systems engineers, firmware developers, architects, and product engineering teams to align hardware designs with broader system requirements. - Laboratory integration and testing: Support hardware integration, lab testing, debugging, and troubleshooting activities to validate performance in practical operating environments. - Physical design support: Contribute to physical design and implementation flows, including RTL-to-GDSII processes and signoff activities, where applicable. - Continuous improvement and technical guidance: Apply industry best practices, explore design improvements, and share technical expertise with colleagues. Depending on project needs, provide mentorship to junior engineers. Requirements We are looking for a highly experienced hardware design engineer with strong digital design fundamentals, hands-on ASIC and FPGA implementation experience, and the ability to solve complex technical challenges.