RET Layout/Mask Engineer

Change the world. Love your job. Texas Instruments is in an exciting era of growth and innovation, and our Advanced Technology Development (ATD) organization is at the center of it — developing the 28nm process technologies that will define TI’s next generation of analog and embedded processing capabilities. As part of ATD, you won’t just support production — you’ll create the technology that makes it possible. Our engineers are working at the leading edge of computational lithography, Resolution Enhancement Techniques, and advanced process integration, solving the fundamental patterning and process challenges that determine whether a 28nm technology can be manufactured at scale and at yield. The work done in ATD directly enables fabs that will manufacture tens of millions of analog and embedded processing chips every day — supporting customer demand for decades to come. We’re committed to responsible, sustainable semiconductor manufacturing and to building a diverse, technically excellent team that drives meaningful impact across the industry. In this role, you’ll work at the intersection of fundamental research and high-volume manufacturing, turning process innovations into production-ready technologies that power electronics everywhere.As a Resolution Enhancement Techniques (RET) Layout Engineer, you will architect new TI products and make our customers' visions a reality. You will define, design, model, implement, and document analog, digital, and RF integrated circuits (ICs). Responsibilities will include, but are not limited to: Create layouts for setup, evaluation, and monitor of lithography/etch wafer processes.Work with fabrication process engineering and integration teams to determine specifications.Use design rules and/or existing layouts to create/modify test features.Maintain a list of measurement coordinate locations.Support and interaction for all fabs and technologies required.Create layouts for OPC development/monitor.Work with other RET engineers on layout and floor plan of test reticles for OPC model calibration and recipe development.Work with RET engineers to layout scribe modules for OPC model calibration/testing.Create layouts for reticle measurement and disposition.Work with other RET engineers and the PDK team to define specifications.Maintain a list of measurement coordinate locations.Work with RET, scribe, and design teams to create rules for layout placement.Develop and implement automation for producing layouts.Why TI?Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TIBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits hereAbout Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com. Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws. If you are interested in this position, please apply to this requisition. TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.Minimum qualifications:Bachelors in Electrical Engineering, Physics, Computer Science, Chemistry or related degreeProficiency with EDA layout tools (Cadence suite, Synopsys, etc.) and scripting (e.g., Python, SKILL, Perl)5+ years of experience in Layout/Mask design.Preferred qualifications:Hands-on experience in design or PDK development with direct experience at a semiconductor companyExcellent problem-solving, analytical, and communication skills for cross-team collaborationExperience working with PG flowsStrong lithography knowledgeOPC experienceFull timePosting Date: 2026-06-15