Package Design Rule Owner (DRO)
$141.91k - $269.1kDormont Manufacturing Co
Job Details: Intel Foundry Technology Development is seeking an experienced Package Design Rule Owner (DRO) to join our Advanced Design and Customer Enabling (ADCE) Package team to support a broad range of product families. Key Responsibilities In this role, your responsibilities will include but not be limited to: The Package Substrate Design Rule Owner (DRO) is responsible for definition, validation and deployment of design rules for package substrate design. The DRO collaborates with product design, substrate manufacturing and package assembly to identify and drive design rules that enable competitive product designs that meet cost and manufacturability requirements. A key part of this role is being involved from the earliest stages of technology and product concept through to product design tape out. The DRO works across product families to drive a consistent Design Rule strategy and a forward‑looking, industry‑leading Design Rule roadmap. This position involves working with cross‑disciplinary and cross‑organizational stakeholders and interfacing directly with product designers. Interaction with external suppliers and customers can also be expected in this role. Qualifications Minimum Qualifications: US Citizenship is required. Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph. Bachelor’s degree in Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Material Science, or a related STEM field. 6+ years of experience with a Bachelor’s degree, 4+ years with a Master’s degree, or 2+ years with a PhD. 2+ years in semiconductor fabrication processes and packaging technologies. 2+ years of experience in package substrate physical design, or thermo‑mechanical and electrical performance, or substrate manufacturing and assembly process, or a combination of these areas. Preferred Qualifications: Active US Government TS/SCI Security Clearance with Polygraph. Expertise in advanced packaging architectures such as EMIB and Foveros. 5+ years of strong analytical and problem‑solving skills: identifying, isolating, and debugging issues and providing creative solutions. Ability to work independently and at various levels of abstraction. 5+ years of strong organization, time management, and communication skills and self‑motivated individual. Good understanding of IC Packaging. Strong communication skills and the ability to work with others. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, Arizona, Phoenix Benefits We offer a comprehensive compensation package that includes competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation. Annual salary range for U.S. locations: $141,910.00 – $269,100.00. This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. (Work model details may change.) Intel is committed to Responsible Business Alliance compliance and ethical hiring practices. Candidates should never be required to pay recruitment or medical‑examination fees as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected under local law, regulation, or ordinance. #J-18808-Ljbffr Dormont Manufacturing Co
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