Digital Verification Engineer

About Us:
At *** (
*** | Connected World, Connected Experiences
), we live the philosophy of connected world and connected experiences. We thrive on change that is powered by the intelligent symphony of technology and humans designing meaningful and sustainable experiences. Consumer 'experiences' are driving and disrupting industries like never before. Businesses must build seamless yet simple enterprises that collaborate, synergize, and drive the change. Change that connects us all and empowers us to deliver experiences that span across the digital, the physical, the convergent, and everything in between. That's when truly connected experiences manifest.
Extraordinary is when experiences come together - a continuous convergence of digital technologies, touchpoints, and most importantly people. It's time to reimagine, reinvent, and revolutionize business models
operations as well as to transform enterprises into living, breathing, and connected businesses. We are the Digital Change makers who strive to change the way the world, communities, businesses, and humans interact digitally. We are harnessing the power of change, brought in by technologies, that makes it the most exciting time to be alive in human history. Our universe, as we build it, disrupt it, and redesign it, is powering the digital change.
*** represents the connected world, offering innovative and customer-centric information technology experiences, enabling Enterprises, Associates, and the Society to Rise. It has 150,000+ professionals working for 1000+ Global Customers (including Fortune 500 companies) in 90 Countries. We're part of the esteemed Mahindra group, headquartered in India. Under a new CEO, *** is committed to a transformative journey with 'Scale @ Speed' as our guiding principle.
Job Title: Digital Verification Engineer
Location: Santa Clara, CA
Onsite/ Hybrid/ Remote: Onsite
Duration: 12 months
The payrate is ***/hr. - ***/hr. c2c
Minimum Qualifications
The ideal candidate should have a BS/MS in Electrical Engineering 8+ years of experience in hands on digital design verification/Mixed signal Co-simulation in ASIC/SOC products.
Advanced knowledge of HVL methodology UVM/OVM
Solid verification skills in problem solving, constrained random testing, and debugging
Experience in writing scripts in languages such as Perl or Python
Experience in defining coverage space and writing coverage model a plus
Experience with SystemVerilog Assertion SV plus
Familiar with design involving AMBA/APB, AHB, AXI buses
Familiar with serial interface protocols SPI/I2C/I3C/UART/MDIO/JTAG
Excellent oral and written communication skills.
"*** is an Equal Employment Opportunity employer. We promote and support a diverse workforce at all levels of the company. All qualified applicants will receive consideration for employment without regard to race, religion, color, sex, age, national origin, or disability. All applicants will be evaluated solely based on their ability, competence, and performance of the essential functions of their positions with or without reasonable accommodations. Reasonable accommodations also are available in the hiring process for applicants with disabilities.
Candidates can request a reasonable accommodation by contacting the company ADA Coordinator at