Design Engineer I

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform… As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug. A bonus, this individual will have cross functional teams’ interactions not only within our group; but across Cadence and the multiple BU involved in our developments. Key responsibilities Define and implement SoC level DFT architecture for large and complex designs. Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG. Perform DFT insertion, verification, and coverage analysis at block and SoC levels. Drive pre-silicon DFT sign-off, including DRC closure and coverage targets. Support post-silicon debug, failure analysis and yield learning. Collaborate with RTL, verification, physical design and operation teams. Qualifications BS degree At least 3 years of hands-on experience in SoC DFT. Must-have skills: Strong expertise in SCAN, ATPG, MBIST. Experience with pre-silicon validation and post-silicon debug. Strong problem solving and debugging skills. Ability to work effectively in a cross-functional engineering environment. Good-to-have skills Scripting experience (TCL, Perl, Python or equivalent) for flow automation and analysis. Experience with IP-level DFT integration and reuse. Exposure to low-power DFT considerations and complex clocking architectures. Familiarity with manufacturing test flows and silicon yield improvement. The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Benefits paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical, dental and vision plan options and more. Equal Employment Opportunity Policy Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact View email address on click.appcast.io. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr