Physical Design Engineer

Tsavorite Scalable Intelligence is building a new foundation for AI computing. We design silicon, systems and software that work as one, bringing together general‑purpose processing, AI acceleration, and scalable memory in a single architecture. From edge devices to data centers, our goal is to make advanced AI more powerful, efficient, and accessible. Our founding team has a track record of shipping the highest performance silicon and we have engineering teams in the US and India. We are looking for curious, driven people across disciplines who want to turn ambitious engineering into real products and help shape how the world computes. Job Summary We are seeking an experienced Physical Design Engineer to drive implementation and signoff of complex, multimillion‑instance, high‑speed SoC subsystems on sub-5nm nodes. You will own convergence end to end across synthesis, place and route (PnR), timing, physical verification, and power delivery network. Technical Skills & Expertise Strong hands‑on expertise across physical design: floorplanning, power planning, placement, CTS, routing, and timing/PPA optimization. Hands‑on experience with high‑performance designs at sub‑5nm nodes. Proven ability to push frequency using custom PnR techniques. Expert in STA and ECO generation across PnR steps. Independently debugs and resolves flow, tool, and design issues. Experience with hierarchical subsystem implementation, including partitioning, budgeting, block abstraction, and top‑level physical integration. Expert with industry‑standard tools: Innovus, Tempus, “Cadence tool suite" Track record of contributing to physical design flows and methodology. Strong automation skills in TCL, Perl, and Python across implementation steps. Experience leading and mentoring engineers, and working across design, STA, and signoff teams. What You'll Drive & Bring to the Role Lead RTL-to-GDS implementation for complex SoC, subsystem, and chiplet designs. Own execution from floorplan through placement, CTS, routing, optimization, and signoff (timing, physical verification, IR/EM). Define implementation strategy and drive frequency, power, area, and complexity trade‑offs against product targets and schedule. Drive physical design methodology for advanced nodes. Partner with RTL architects to resolve timing, congestion, area, and power bottlenecks early. Work closely with signoff teams to drive overall design convergence. Required Qualifications BS or MS in Electronics/Electrical Engineering. 5+ years Why Join Us? Own. Innovate. Make an Impact. Join a talented team building next‑generation compute solutions and working on cutting‑edge technology. Take ownership, collaborate with great engineers, grow your skills, and make an impact in a culture that values innovation and teamwork. Competitive Compensation aligned with industry benchmarks. Comprehensive Health Insurance covering employees and eligible dependents. Stock Options & Ownership Opportunities. #J-18808-Ljbffr