Physical Design Engineer
Value Innovation Labs Inc.
We're Hiring: Physical Design Engineer - 3DIC We are looking for an experienced Physical Design Engineer - 3DIC Own the end-to-end RTL-to-GDSII physical design flow. Perform synthesis, floorplanning, placement, routing, and Clock Tree Synthesis (CTS). Support 3D-IC integration , heterogeneous integration, multi-die assemblies, and TSV planning. Drive timing closure, Static Timing Analysis (STA), IR drop, and Electromigration (EM) analysis. Develop and optimize automation scripts using Tcl, Python, or Perl. Collaborate with IP teams and foundry partners on advanced-node designs. 5-10 years of hands-on ASIC/SoC Physical Design experience. Experience with multiple full-cycle tape-outs at advanced nodes ( 5nm, 3nm, or 2nm ). Strong knowledge of MMMC, signal integrity, timing closure, and 3D packaging technologies. Expertise in industry-standard EDA tools such as Cadence Innovus, Tempus, Voltus or Synopsys ICC2, PrimeTime . Tcl scripting is mandatory ; Python or Perl experience is a plus. Important: This is a one-time, full-time hiring requirement only . C2C candidates will not be considered. #J-18808-Ljbffr Value Innovation Labs Inc.
Vacancy posted 1 day ago
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