DDR PHY Design Engineer - RTL, Timing & Silicon Bring-up
Apple Inc.
Apple Inc. is seeking a DDR Design Engineer to join the DDR PHY design team in Beaverton, OR. You will contribute to high-performance, low-power digital designs from concept through silicon bring-up, working closely with architecture, verification, and validation engineers. The role emphasizes RTL in Verilog/SystemVerilog, formal verification, timing closure, and power characterization, with a strong focus on testability and DFT readiness. Prior DDR PHY experience is a plus. #J-18808-Ljbffr Apple Inc.
Vacancy posted 1 day ago
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