Senior ASIC Designer: Memory Acceleration for AI Workloads
Netpreme
Netpreme is seeking experienced Senior ASIC Designers to lead RTL design of IPs, subsystems, and SOCs for its silicon roadmap. Bring 5+ years in ASIC/SOC design, Verilog/SystemVerilog, and a track record of design leadership. You will collaborate across architecture, verification, physical design, firmware, DFT, and post-silicon domains, interface with vendors, and drive designs toward aggressive performance, power and area goals in an early-stage AI/datacenter product. #J-18808-Ljbffr Netpreme
Vacancy posted 4 days ago
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