Senior Physical Design Engineer, FPGA/SoC (San Jose)
Altera
Altera Corporation is seeking a Senior Physical Design Engineer in San Jose, CA to lead physical implementation of IP/SoC from RTL to GDSII and drive timing closure, power optimization, and design sign-off for next‑gen FPGA products. You will collaborate with RTL, CAD, and verification teams to deliver high‑quality silicon while improving physical design methodologies and automation. A strong background in CTS, STA, and multi‑domain design is required. #J-18808-Ljbffr
Vacancy posted 6 hours ago
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