Senior SoC Network Subsystem Architect

About The Role The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. Job Details Senior SoC Network Subsystem Architect – Lead the architecture of high-performance network subsystems for next-generation IPU/DPU platforms. Focus on designing scalable, programmable networking pipelines that support hyperscale and cloud data center workloads. Responsibilities Own end-to-end NSS architecture, including packet processing pipelines, protocol engines, and interface datapaths. Architect high-performance packet pipelines supporting hundreds of millions of packets per second throughput and processing flows. Drive architectural direction for programmable versus fixed‑function pipeline balance and future extensibility. Specify network subsystem pipeline scaling strategies and define multi-generation NSS architecture roadmap. Lead design decisions for pipeline partitioning, feature scalability, and backward compatibility. Architect advanced scheduling frameworks (per‑flow shaping, multi‑level scheduling, traffic class isolation). Define QoS models to support multi‑tenant workloads, virtualization, and service chaining. Define architecture for telemetry, performance counters, and real‑time observability of pipeline behavior. Define architecture support for field debug, failure triage, and large‑scale deployment monitoring. Collaborate across SoC, compute, memory, SW/FW, validation, and customer teams to drive architecture closure. Interface with external customers to translate workload requirements into NSS architecture decisions. Lead architectural reviews and influence cross‑team technical direction. Behavioral Traits Strategic thinker: Ability to define long‑term architecture vision and align stakeholders. Technical leadership: Influences across teams without direct authority. Problem solver: Approaches complex system challenges with structured thinking. Collaboration: Builds strong partnerships across engineering disciplines. Customer‑focused mindset: Translates real‑world workload needs into solutions. Adaptability: Navigates ambiguity and evolving technical requirements. Ownership mindset: Drives initiatives from concept through execution. Minimum Qualifications Bachelor’s degree in Electrical/Computer Engineering, Computer Science or related degree with 7+ years of experience. 7+ years of experience in networking ASIC / SoC / IPU / DPU architecture. High‑speed packet processing pipelines. Experience in system‑level architecture tradeoffs. Defined and delivered architecture for large‑scale data center networking systems. Preferred Qualifications Programmable datapath architectures (P4, pipeline microcode, or hybrid models). AI/HPC scale‑out networking and congestion control architectures. Transport protocols offloads. QoS, scheduling, and multi‑tenant isolation. Familiarity with coherent or shared‑memory offload models (e.g., CPU‑IPU integration). Experience with hyperscaler deployments or customer co‑design engagements. Benefits Intel offers a competitive compensation package, including pay, stock bonuses, and benefit programs such as health, retirement, and vacation. Annual Salary Range for this position in the US: $164,470.00 – $269,100.00 USD. The role is eligible for a hybrid work model. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Additional Information Intel does not charge any fees during the hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. This role is eligible for hybrid work and is located in Santa Clara, California, with additional locations across the United States. #J-18808-Ljbffr Intel