Lead RTL Design Engineer for Energy-Efficient Dataflow SoC
Efficient Computer
Efficient Computer in Austin, TX is building power-efficient edge and data-center compute with its Fabric architecture. The Lead RTL Design Engineer will own microarchitecture definition and RTL implementation across the dataflow fabric, memory subsystem, and NoC, driving performance, power and area targets while collaborating with architects, DV, and firmware teams. The role offers ownership of architecture specs, tape-out readiness, and a path from initial product development to market #J-18808-Ljbffr Efficient Computer
Vacancy posted 4 days ago
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