Senior CPU RTL Front End Designer

: Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Poughkeepsie, NY, USA; Portland, OR, USA .

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will help serve as a bridge between Instruction Set Architecture (ISA), software, and hardware design within the vertically integrated environment. You will be responsible for interpreting complex ISA specifications and collaborating with design and design verification (DV) teams. Your expertise will ensure our microarchitecture is not only ISA-level compliant but also meets security expectations, achieves functional correctness, and delivers exceptional performance. You will play a key role in identifying and defining the architecture for new hardware-software features, delivering from concept to implementation.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Interpret complex ISA and software requirements, guiding design and Design Verification (DV) teams to ensure microarchitectural compliance, functional correctness, and security.
• Identify and define architecture for new hardware/software features, collaborating with cross-functional teams for solutions.
• Lead analysis and propose solutions to meet ISA compliance, functional correctness, and performance and power goals.
• Research and evaluate emerging CPU architectures, influencing long-term decisions and product roadmaps.
• Serve as a subject matter expert, providing architectural guidance and standard procedures to elevate team capabilities.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.