Analog IP Design Execution Manager

Overview The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry defining analog and mixed signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. As an IP execution leader, you will lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology. This IP execution leader role will be responsible for the following: Responsibilities All aspects of the integrated IP planning, execution, and delivery from initial engagement with SOC partners, conceptual planning and tech readiness, pre-silicon execution, post-silicon validation and launch. This leader coordinates across IP domains (architecture, analog, logic, validation) and key SOC swim lanes to deliver IP releases on time and with committed content and quality. Knowing enough detail about the execution of the IP program that you can adeptly speak to program status and risks using data, metrics, and trends. Drawing on prior design experience, identify technical problems and take the lead to drive solutions. Ensuring appropriate progress against schedule, recommend recovery actions and mitigate issues. Drive efficient, effective, and transparent decisions to keep IP execution tracking positively toward aggressive and achievable deliverables. Clear, appropriately leveled communication to a range of audiences spanning engineers, technical leaders, and executives. Establishing productive, collaborative relationships with peers, partners, and stakeholders spanning SOC, IP design, and post-silicon validation teams. Maintaining strong connections with other IP execution leads and partners located in both the US and globally. Conduct retrospective reviews to drive continuous improvements in execution efficiency and product quality. Driving results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. This is an on-site role and you are expected to work in the office at least 4 days per week. Qualifications Strong results orientation and great aptitude for problem-solving. Ability to see a challenge on the horizon and plan for it. You are skilled and comfortable facilitating direct and open communication. You work naturally and readily with a wide range of contributors: technical leads, manager peers, partner teams, senior technologists, executives, and other organizations. You can articulate ideas and key messages succinctly. Demonstrated success leading large-scale, cross-functional programs with aggressive timelines and complex external dependencies. Ownership mindset with a high degree of urgency and accountability for execution results and customer success. Solid understanding of the end-to-end silicon lifecycle, from architectural definition through production qualification and release. Familiarity with AI/ML-driven design productivity techniques, automation frameworks. Proven experience executing complex mixed-signal and/or high-speed serial IP development in advanced semiconductor process nodes. Excellent communication, documentation, and presentation skills to audiences ranging from individual contributors to technical leaders and executives. Minimum Qualifications Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 8+ years of experience 5+ years of experience managing technical execution for silicon projects. Solid foundational knowledge of analog design principles—noise, jitter, matching, stability, and linearity. Experience in analog design and IP delivery. Preferred Qualifications Master's degree in Electrical Engineering, Electronics Engineering, or related field with 6+ years of experience 8+ years of experience managing technical execution for silicon projects. Proven expertise in analog IP development and delivering from concept to launch with hands on experience in analog circuit design, mixed signal logic and validation, physical design. Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits. Deep knowledge of high speed serial IO technologies such as PCIe/CXL and USB and of die to die technologies such as UCIe, BoW, HBM. Job Type Experienced Hire Shift Shift 1 (United States of America) Locations Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Business Group The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $190,610.00 - 269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change. Additional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr Intel