System-on-Chip Design Engineer
Belcan
Job Description
Chip Design Engineer
\nAre you passionate about digital silicon design and verification? We're looking for an experienced Chip Design Engineer to help shape and validate realistic semiconductor design training environments while working across the full chip design lifecycle.
\n \nLocation: Remote / Hybrid (as applicable)
\nExperience: 10+ Years
\nEducation: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent
\n \nKey Responsibilities
\n✅ Review and validate RTL design, verification, and physical implementation tasks for technical accuracy and realism.
\n✅ Support development of chip design training environments across design, verification, and physical implementation domains.
\n✅ Assess solutions and define technical skill benchmarks for engineering tasks.
\n✅ Collaborate closely with building teams, model training teams, and domain experts.
\n✅ Drive continuous improvement of task quality, realism, and engineering standards.
\n✅ Explain design decisions, methodologies, and tradeoffs involving power, performance, area, and verification.
\n \nRequired Qualifications
\n✔ 10+ years of Digital ASIC or SoC design experience.
\n✔ Strong expertise in:
\n- \n
- RTL Design \n
- SystemVerilog Design & Verification \n
- SystemVerilog Assertions (SVA) \n
✔ Hands-on experience with Synopsys EDA tools:
\n- \n
- VCS \n
- Design Compiler \n
- IC Compiler II / Fusion Compiler \n
- PrimeTime \n
✔ Deep understanding of front-end design, verification, and physical design flows.
\n✔ Ability to communicate complex technical concepts and engineering tradeoffs effectively.
\n✔ Strong project management, stakeholder engagement, and collaboration skills.
\n \nPreferred Qualifications
\n⭐ Full RTL-to-GDSII flow experience.
\n⭐ UVM-based verification environment development.
\n⭐ Static Timing Analysis (STA).
\n⭐ Low-Power Design (UPF).
\n⭐ Design for Testability (DFT).
\n⭐ Experience with industry-standard EDA tool suites.
\n \nWhat We're Looking For
\nWe're seeking a detail-oriented engineer who can combine strong technical expertise with excellent communication and collaboration skills. The ideal candidate will be comfortable working independently, partnering with cross-functional teams, and driving excellence in chip design training and evaluation programs.
\n \nInterested candidates can apply directly or reach out via DM.
\n#Hiring #ChipDesign #ASIC #SoC #RTLDesign #SystemVerilog #Verification #SVA #UVM #PhysicalDesign #VLSI #SemiconductorJobs #PrimeTime #DesignCompiler #VCS #ICCompilerII #FusionCompiler #STA #DFT #EngineeringJobs
$85 - $93.29 per hour
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