Senior Chip Design Engineer : 26-02794

Job Description

\nPrimary Skills: Digital ASIC design (advanced), SystemVerilog verification (advanced), RTL to GDSII flow (intermediate), Synopsys VCS (advanced), Synopsys Design Compiler (advanced)\n
\nContract Type: W2\n
\nDuration: 3 Months with possible extension\n
\nLocation: Bellevue, WA ()\n
\nPay Range: $85.00-$93.29 Per hour\n
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Job Summary:
This role involves designing and verifying digital silicon chips, ensuring that training environments accurately reflect real-world chip development processes. You will critically assess design tasks, establish standards for correct solutions, and collaborate with teams building these training simulations. Your expertise will be crucial in identifying discrepancies between simulated tasks and actual engineering practices.\n
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Key Responsibilities: \n

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• Design and verify digital silicon for complex integrated circuits.
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• Develop and validate realistic chip design training scenarios.
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• Review RTL code and assertion-based verification strategies.
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• Analyze and define quality benchmarks for design solutions.
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• Partner with training development teams to enhance realism.
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Must-Have Skills: \n

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• Extensive experience in digital ASIC or SoC design.
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• Proficient in SystemVerilog for both design and verification.
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• Solid understanding of the RTL to GDSII implementation flow.
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Industry Experience:  Experience in the semiconductor industry, with a focus on digital ASIC development and verification across the entire design lifecycle, is highly valued.\n
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ABOUT AKRAYA
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