Senior ASIC Clocks Architect - RTL & GPU/CPU Timing
Jobleads-US
NVIDIA Corporation is seeking a Senior ASIC Design Engineer for the Clocks IP team in Santa Clara, CA. You will architect clock domains, collaborate across GPU/CPU teams, and push for performance, power, and area improvements while delivering robust clock RTL to verification and DFT groups.
You should have a BS in EE (MS preferred) and 3+ years in RTL design and verification, with strong Python skills and awareness of sub-micron silicon challenges.
#J-18808-Ljbffr Jobleads-USVacancy posted 5 hours ago
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