Senior RTL Design Engineer - ASIC Compute for SoC
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Google in Sunnyvale, CA is seeking an experienced ASIC Design Engineer to develop custom silicon for data-center products, focusing on efficiency and integration. You will define microarchitecture, write SystemVerilog RTL, and collaborate across software, architecture, and physical design teams.
The role emphasizes power, performance, and area optimizations, validation planning, and timing closure to meet aggressive hardware requirements.
#J-18808-Ljbffr Jobleads-USVacancy posted 11 hours ago
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