SOC IP Methodology Engineer - Custom SOC

What you will be doing Responsible for developing and optimizing semi‑custom RTL‑to‑GDS methodologies, working with internal and external collaborators and IP vendors on SOC/IP requirements and driving technology alignment across them. Act as a hands‑on domain expert, traversing from synthesis to final design closure (timing and layout) using the latest EDA technologies and capabilities. Work with customers on SOC/IP development processes, IP quality and handoff requirements for QA, ensuring smooth integration and high‑quality analysis flows. Drive, review, and cultivate development processes to assure top quality work to and from IP customers and SOC engineers. Lead technical design reviews, ensure defined processes are followed, identify and mitigate risks, and continuously improve development processes with innovative tools and procedures. Be responsible for results/handoffs to and from customers, methodology solutions and schedule plans. Drive early PPA on customer IP, conduct what‑if experiments to support KPI targets, and analyze and solve critical issues. Collaborate internally and externally to conduct floorplan experiments, drive area estimates and evaluate solution tradeoffs. Work with the Nvidia PD design methodology team to develop best methodologies for integrating external customer IP. Collaborate with external ASIC companies if outsourcing of certain Nvidia design components is required. What we need to see Masters with 8+ years (or BS/Equivalent with 10+ years) of experience in relevant skill areas. Extensive leadership experience as a methodology and technical expert in physical design, working with internal and external partners. Experience in an SOC development and customer‑focused environment with excellent interpersonal skills. Experience handling complex IP ecosystems involving both internal and external partners; exposure to IP‑XACT or similar infrastructure is a plus. Proven hands‑on experience with RTL‑to‑GDSII tool flows and physical design and analysis tools from EDA vendors such as Cadence, Synopsys, Mentor (CDC, LP Checks, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT‑SI, Tempus, Redhawk), etc. Understanding of the full flow (including DFT, BIST) to integrate customer and third‑party IP and drive program alignment. Proven ability to optimize methodology and flows for high productivity, design optimization and innovation. Strong background and knowledge in synthesis, CTS, power optimization, placement and route methods and timing convergence for high‑performance designs such as CPU, GPU and machine‑learning IPs. Strong scripting skills in Python, Perl and Tcl, plus excellent soft skills. RTL2GDS experience with high‑performance ARM cores, Serdes, DDR, GPU or machine‑learning IP experience is a plus. Benefits and Compensation Compensation includes a base salary ranging from $168,000 to $264,500 for Level4 and $196,000 to $310,500 for Level5, adjusted based on location, experience, and comparable positions. Additional equity and benefits are provided. Applications will be accepted until January24,2026. Equal Opportunity NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA Gruppe