Senior RTL Verification Engineer — SystemVerilog & UVM
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Delos Data Inc. in Silicon Valley is seeking an experienced RTL Verification Engineer to ensure the functionality of complex digital designs for ASIC/FPGA platforms.
You will build robust verification environments, implement coverage-driven plans, and collaborate with RTL designers to deliver reliable silicon. The ideal candidate has hands-on SystemVerilog, UVM, and Python experience and will drive verification from planning through closure.
#J-18808-Ljbffr Jobleads-USVacancy posted 2 days ago
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