Senior FPGA Timing Engineer - STA & Closure Lead
Altera Corporation
Altera Corporation in San Jose, California, is seeking a Timing Engineer to lead timing activities across a subsystem, partnering with Design, Architecture and Physical Design to achieve timing convergence from implementation to sign-off. The role requires strong STA, timing constraints, and advanced sign-off methods, with experience on modern process nodes; you will drive timing budgets, clock planning, and ECOs, and collaborate with RTL, PD and full-chip teams. #J-18808-Ljbffr Altera Corporation
Vacancy posted 2 days ago
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