ASIC Verification Engineer

ASIC Design Engineer III

This role has been designed as 'Onsite' with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world. Our culture thrives on finding new and better ways to accelerate what's next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

ASIC Design Engineer – Networking SoC

HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build our world-class routers and switches.

Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.

Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards.

Position Summary

We are seeking a highly motivated RTL Design Engineer with approximately 5 years of industry experience to join our networking silicon development team. The successful candidate will be responsible for the microarchitecture, RTL implementation, integration, and bring-up of high-performance networking IPs and subsystems used in next-generation switch, router, SmartNIC, DPU, and AI networking products.

The ideal candidate possesses strong digital design fundamentals, hands-on RTL development experience, and familiarity with modern networking protocols and high-speed interfaces.

Responsibilities

• Define microarchitecture specifications based on system and architectural requirements.
• Develop high-quality RTL using System Verilog/Verilog for networking Datapath and control-plane logic.
• Design and implement networking blocks or parts of the blocks such as (Depending on the needs):
  • Packet processing pipelines
  • DMA engines
  • Traffic management
  • Buffer management
  • Queue managers
  • Flow-control mechanisms
  • Statistics and monitoring engines
• Collaborate with architecture, verification, physical design, and firmware teams throughout the development cycle.
• Perform RTL linting, CDC analysis, synthesis, and timing closure support.
• Develop design documentation including architecture specifications, microarchitecture documents, and implementation guides.
• Support FPGA prototyping and post-silicon bring-up activities.
• Analyze and debug functional issues found during simulation, emulation, FPGA validation, and silicon bring-up.
• Participate in design reviews and contribute to engineering best practices.

Required Qualifications

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
• 5+ years of ASIC/SoC RTL design experience.
• Strong expertise in:
  • SystemVerilog
  • Verilog
  • Digital logic design
  • Finite State Machines (FSMs)
  • Clock-domain crossing (CDC)
  • Reset-domain crossing (RDC)
  • Low-power design concepts
• Familiarity with AMBA protocols:
  • AXI4
  • AXI-Stream
  • APB
  • AHB
• Understanding of ASIC design flow including:
  • Lint
  • CDC
  • Synthesis
  • STA fundamentals
• Experience using industry-standard EDA tools from Synopsys, Cadence, or Siemens.

Nice to have

• Experience with networking protocols such as:
  • Ethernet (10G/25G/100G/400G/800G)
  • TCP/IP
  • RDMA
  • PCIe
  • CXL
• Experience designing packet-processing pipelines.
• Knowledge of high-speed SerDes architectures and MAC/PCS interfaces.
• Experience with FPGA prototyping and hardware validation.
• Exposure to performance modeling and architectural tradeoff analysis.

Desired Skills

• Strong debugging and problem-solving abilities.
• Ability to work effectively in a cross-functional team environment.
• Excellent written and verbal communication skills.
• Self-driven with a strong sense of ownership and accountability.
• Ability to drive complex technical tasks from concept through silicon.

Key Success Metrics

• Delivery of clean, synthesizable RTL with minimal functional escapes.
• First-pass silicon success.
• Efficient closure of design quality metrics including lint, CDC, and timing.
• Successful execution of networking subsystem features within project schedules.
• Strong collaboration across architecture, verification, and implementation teams.

The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.

– United States of America: Annual Salary USD 120,000 - 243,000 in California

The listed salary range reflects base salary. Variable incentives may also be offered.