Staff/Principal RTL Design Engineer for AI Inference ASIC
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Acceler8 Talent is seeking a hands-on Staff, Senior Staff, or Principal RTL Design Engineer for a seed AI hardware startup building a dedicated LLM inference ASIC. You will own a substantial RTL scope and translate microarchitecture into synthesizable RTL, collaborating with verification and physical-design teams near Palo Alto.
Strong Verilog/SystemVerilog skills are essential; AI accelerator or inference ASIC experience is preferred, with deep digital-silicon know-how and a proven track record
#J-18808-Ljbffr Jobleads-USVacancy posted 9 hours ago
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