Sr. Design Verification Engineer

Job Description

Senior Design Verification Engineer – Complex SoC

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Engagement: Contract, 6–9 months with potential extension

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Location: 100% Remote

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Geography: USA preferred; highly qualified candidates in other locations will be considered

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Position Overview

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We are seeking an exceptionally strong Senior Design Verification Engineer to support the verification of a highly complex, advanced SoC.

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This is a hands-on technical role for an experienced verification engineer who can architect, develop, and enhance sophisticated UVM-based verification environments and testbenches . The ideal candidate has spent significant time verifying complex SoCs and SoC subsystems and is comfortable working independently on challenging verification problems.

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This is not a junior or primarily test-execution position. We are looking for an engineer capable of developing verification infrastructure and testbenches for large, complex designs.

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Required Qualifications

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• 10–15+ years of Design Verification experience
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• Exceptional expertise in SystemVerilog and UVM
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• Extensive hands-on experience developing UVM testbenches and verification environments from the ground up
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• Strong experience verifying highly complex SoCs and SoC subsystems
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• Demonstrated ability to develop scalable verification architectures, including:
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• UVM agents, drivers, monitors, sequencers, and scoreboards
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• Reference models and checkers
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• Functional coverage models
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• Constrained-random stimulus
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• Assertions and protocol checking
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• Strong experience with SoC-level and subsystem-level verification
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• Deep understanding of verification planning, test development, coverage closure, regression analysis, debugging, and root-cause analysis
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• Ability to debug complex interactions across multiple IP blocks, interfaces, clocks, resets, and system-level scenarios
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• Strong understanding of common SoC architectures, interfaces, memory systems, interconnects, and peripheral subsystems
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• Ability to work independently in a distributed, remote engineering environment
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Highly Desired Experience

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Hands-on verification experience with one or more of the following is highly desirable:

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• PCI Express (PCIe), preferably Gen5 or later
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• UCIe
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• High-speed Ethernet
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• Complex SoC interconnect and subsystem verification
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• Multi-core or heterogeneous SoC architectures
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• High-speed interfaces and protocol verification
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Ideal Candidate

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The ideal candidate is a deeply technical verification engineer who has worked on large, sophisticated semiconductor designs and understands the challenges associated with verifying interactions across multiple SoC subsystems.

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We are particularly interested in engineers who have taken ownership of major portions of a verification environment—not simply maintained existing tests—and who can quickly understand an unfamiliar architecture, identify verification requirements, and build robust UVM infrastructure to verify it.

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This role requires someone who can operate with a high degree of technical independence while collaborating effectively with RTL designers, architects, verification engineers, and other members of a geographically distributed engineering team.

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Engagement Details

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• 6–9 month initial contract
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• Potential for extension based on project requirements and performance
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• 100% remote
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• USA-based candidates strongly preferred
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• Exceptional candidates in other locations will also be considered
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