Interconnect Design Engineer

Job Description SiFive is looking for a staff level hardware engineer who is passionate about designing industry‑leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs across a broad variety of vertical applications. The engineer will build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP using the Chisel hardware construction library embedded in the Scala language. The Challenge Design the best interconnect IP in the world, based on the revolutionary open RISC‑V and TileLink architectures; master the art of designing hardware as configurable generators in a domain‑specific software language for elaborating circuits; work in a fast‑paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance. Responsibilities Architect, design and implement an enhanced TileLink interconnect, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel. Implement RTL generators such that elements self‑configure to optimally connect to each other. Enhance future designs to provide higher performance and more efficient multi‑core and multi‑system coherence. Design extensive configurability as a first‑class consideration. Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software. Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans. Ensure knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design. Qualifications Knowledge of cache and cache coherency architectures and concepts. Experience with NoC or other interconnect fabrics. Familiarity with industry‑standard bus protocols (AXI, AHB, APB, CHI). Ability to architect solutions to connect bus fabrics of disparate protocols. Strong software engineering skills/background, including: Object‑oriented, aspect‑oriented, and particularly functional programming. Templated metaprogramming, in any language. Compiler infrastructures, particularly for domain‑specific languages. Data modeling, particularly intermediate representations for optimizing or transforming compiler passes. Test‑driven development, particularly ability to write adaptive unit tests. Proficiency with hardware (RTL) design in Verilog, System‑Verilog, or VHDL. Attention to detail and a focus on high‑quality design. Ability to work well with others and a belief that engineering is a team sport. BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience. Nice to have Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software. Knowledge of RISC‑V architecture. Experience with Git/GitHub, Jira, Confluence. Pay & Benefits Base pay range: $158,760.00 – $194,040.00, varying by location. Variable or incentive compensation and/or equity may be eligible. Comprehensive, competitive benefits package that may include healthcare, retirement plans, paid time off, and more. Additional Information This position requires a successful background and reference checks and satisfactory proof of right to work in the United States of America. Any offer of employment is contingent on verification that the candidate is authorized for access to export‑controlled technology under applicable export control laws. Equal Opportunity Employer SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. #J-18808-Ljbffr SiFive, Inc.