Physical Design Lead, ASIC

Google Sunnyvale, CA, USA Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in physical design, including custom structured datapath implementation. Experience hardening dense compute units (such as dot-product engines, multiplier-accumulator (MACs), multipliers, or arithmetic logic unit (ALUs) into high-frequency, low-power macros. Experience in sub-7nm process nodes (including FinFET and Gate-All-Around architectures), managing the physical density and routing congestion typical of custom datapaths. Preferred qualifications Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with focus on computer architecture. Experience in structured placement methodologies (e.g., relative placement, data-flow driven layout, and customized power-grid stitching for dense blocks). Experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation. Experience with physical design and timing, managing PT-to-PnR timing correlations and metal-fill impacts on dense structures. Expert-level scripting versatility (Tcl, Python, Perl) to build layout automation and structural constraints within standard EDA tools. About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration by developing custom silicon solutions that power Google’s TPU technology. You will lead the design of critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL to GDSII, and manage the full physical design flow. You’ll be responsible for detailed feasibility studies, optimizing performance, power, and area tradeoffs, and improving advanced physical design methodologies to deliver high‑performance, low‑power silicon at scale. US: $192,000 - $279,000 (USD) + 20% bonus target + equity + benefits Responsibilities Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor‑planning, place and route (PNR), timing closure, and physical signoff. Understand math‑intensive micro‑architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure. Develop and improve advanced physical design methodologies and custom implementation recipes, optimizing PPA across complex arithmetic pipeline structures. Manage different PNR tools—Synopsys Fusion Compiler, Cadence (Innovus/Genus), PrimeTime, StarRC, Calibre, Apache Redhawk. Implement and execute key design phases: floor‑planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (DRC/LVS, EM/IR), and final signoff. Lead sub‑chip execution and drive delivery, providing direct technical guidance and mentorship to a small team of engineers to ensure on‑schedule project completion. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. Equity is granted exclusively and discretely by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. #J-18808-Ljbffr Google Inc.