Senior NPI Test Engineer (Semiconductor)

At Elevate Semiconductor, we design high performance analog and mixed signal integrated circuits for automated test equipment (ATE), helping the world's leading semiconductor companies reduce the cost of test while improving speed, accuracy, and efficiency. As a growing, engineering driven company, we offer the opportunity to solve complex technical challenges, collaborate with experienced industry leaders, and make a direct impact on products used across the global semiconductor industry. Elevate Semiconductor is seeking a Senior Test Engineer to lead New Product Introduction (NPI) for precision analog and mixed‑signal integrated circuits used in memory, AI, computing, and high‑performance automated test equipment (ATE) applications. This role owns the production test strategy from first silicon through high‑volume manufacturing and works closely with Design, Product Engineering, Applications, Quality, Operations, and external manufacturing partners to deliver robust, cost‑effective production solutions. Responsibilities Lead NPI activities from first silicon through production release for precision analog and mixed‑signal IC products. Develop complete production test solutions for wafer sort and final test using Teradyne UltraFlex IGXL and associated handlers/probers. Correlate bench measurements with ATE results and establish production test limits using statistical analysis and characterization data. Develop and optimize production test programs for precision DACs, current source/sink products, PMICs, analog interface ICs. Design, debug, and validate load boards, probe cards, sockets, and production hardware in collaboration with external vendors. Drive multisite optimization, parallel testing, throughput improvement, and overall manufacturing cost reduction. Perform silicon debug and root‑cause analysis for design, process, package, and test related issues. Work closely with IC Design during schematic reviews, silicon bring‑up, and Design‑for‑Test (DFT) planning. Support qualification, reliability, HTOL, characterization, and customer qualification activities. Develop production release documentation including correlation reports, GR&R studies, guard‑banding analysis, and manufacturing specifications. Transfer products into OSAT and high‑volume manufacturing while providing engineering support during production ramp. Develop automation tools using Python, JMP, and data analytics to improve engineering productivity and manufacturing quality. Qualifications Bachelor’s degree in Electrical Engineering or related field 6 plus years of experience in semiconductor test engineering, ideally with analog or mixed signal ICs Experience with Teradyne UltraFlex and or Verigy SmartScale or PinScale platforms Understanding of analog testing principles and methodologies Experience with vector translation tools such as Velocity or Test Insight Familiarity with scan testing, JTAG, memory BIST, and loopback techniques Strong troubleshooting skills and attention to detail Strong communication skills and ability to collaborate across teams Preferences Experience with test hardware development including load boards, probe cards, and sockets Exposure to high volume manufacturing environments and offshore vendors Experience with wafer level testing and multi‑site optimization Familiarity with analog simulation tools and testbench correlation Interest in process improvement and test automation Benefits 100% Employer Paid Health Insurance (Medical, Dental, Vision) Unlimited Paid Time Off Performance Bonuses Daily Free Lunch Catered in by Local Restaurants Private Equity Options Retirement Plans Sabbatical Program Tuition Reimbursement Volunteer Days Relocation Assistance Conference Attendance Support Biweekly Phone Stipend Employee Assistance Program The salary range for this role is $106,250.00- $166,750.00 USD/year. Starting salary will be aligned with your relevant experience and demonstrated capabilities during the interview process. Typically, candidates begin at the initial tier of our compensation range, with placement adjusted for candidates presenting extensive directly applicable experience. #J-18808-Ljbffr Elevatesemi