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RTL Design Engineer

Lorven Technologies Inc

Job Title: RTL Design Engineer


Location: San Jose CA - onsite


Position: Contract


Role Overview:


The RTL (Register Transfer Level) Design Engineer translates high-level architectural requirements into digital circuit logic using Hardware Description Languages (HDLs). They build the functional building blocks of chips like ASICs, FPGAs, or SoCs.


Key Responsibilities:

  • RTL Coding: Write clean, synthesizable code in Verilog, SystemVerilog, or VHDL.
  • Microarchitecture Design: Plan how data flows between registers and logical blocks.
  • Quality Checks: Run Lint checks and Clock Domain Crossing (CDC) tests to find syntax errors and prevent data corruption.
  • Power & Timing: Work with physical design teams to meet power targets (using UPF) and timing constraints. [1, 2, 3, 4]
Required Skills:
  • Proficient in Verilog, SystemVerilog, or VHDL.
  • Strong grasp of digital logic design and Finite State Machines (FSM).
  • Familiarity with EDA tools like SpyGlass or JasperGold.
  • Scripting knowledge in Python, Perl, or Tcl.
Vacancy posted 2 days ago
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