Analog Design Engineer

Analog Design Engineer

Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions. You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible.

Job Description

Key Responsibilities

• Design and development of analog and mixed-signal circuits for 3D NAND Flash memory, supporting array operation, peripheral circuitry, and power delivery.
• Drive top-level integration and verification of analog IP within the NAND chip architecture, including interaction with array-level and peripheral power domains.
• Collaborate closely with layout engineers to address dense routing, coupling noise, IR drop, and electromigration challenges specific to 3D NAND layouts.
• Perform circuit simulations, silicon debug, and post-silicon characterization, with focus on array-induced noise, supply droop, and PVT sensitivity.
• Conduct power integrity and noise analysis for NAND-specific stress conditions, including simultaneous wordline/bitline switching, charge pump loading, and peak current events.
• Leverage post-layout RC extraction to evaluate parasitic impacts on wordline, bitline, and power networks, and correlate with silicon behavior.
• Support chip-level power analysis across NAND operating states, including current profiling, peak power characterization, and margin analysis.

Qualifications

Minimum Qualifications

• At least 5 years of relevant experience with a bachelor's degree in Electrical Engineering or equivalent; advanced degree is a plus.
• Strong understanding of analog circuit design fundamentals, including matching, noise, stability, power consumption, and layout-dependent effects.
• Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre, HSPICE, PrimeSim).
• Experience analyzing post-layout simulation results and resolving power- or noise-related issues.
• Strong problem-solving skills with the ability to work independently and across disciplines.
• Excellent written and verbal communication skills, with proven experience in a collaborative engineering environment.

Preferred Qualifications

• Experience with 3D NAND or non-volatile memory design
• Experience correlating simulation results with silicon measurements and Post Si design verification

The compensation range for this role is $121,280 - $194,100. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.