Memory Layout Engineer
Leadic Design
Posted: 6 days ago, Openings: 2, Applicants: Less than 10 Senior Memory Layout Engineer Location: Germany Notice period: Up to 60 days Qualifications Senior Memory Layout Engineer with 5+ years of SRAM Memory Layout experience and expertise in TSMC FinFET (7nm/5nm/3nm/2nm) and Cadence Virtuoso XL/EXL/MXL. Skills highlighted as preferred key skills. Company Founded in 2018, LeadIC has evolved into a trusted partner for global semiconductor companies, supporting the complete chip development lifecycle with deep technical capability. Engineering teams are located across India, Germany, and Canada. #J-18808-Ljbffr Leadic Design
Vacancy posted 5 days ago
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