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Hardware Engineer

SGS Consulting

Job Responsibilities:

  • Design, develop, implement, and validate FPGA-based digital hardware systems
  • Translate functional and algorithmic requirements into optimized VHDL/Verilog architectures
  • Develop and execute functional and timing simulations using HDL test benches
  • Design, develop, and bring up PCBs for radar and embedded hardware systems
  • Integrate FPGA implementations into operational hardware environments
  • Support digital receiver and radar subsystem development
  • Utilize test equipment including RF signal generators, oscilloscopes, and logic analyzers for validation and troubleshooting
  • Perform hardware integration, debugging, testing, and performance optimization
  • Evaluate design tradeoffs related to speed, resources, and system performance
  • Develop and maintain technical documentation for hardware and firmware designs
  • Collaborate with technical teams and stakeholders to communicate results and project status
  • Participate in field testing, data collection, and system evaluation activities

Skills:

  • FPGA Development (VHDL/Verilog)
  • Digital Hardware Design
  • Radar Systems Development
  • PCB Design and Layout
  • Embedded Systems Development
  • Signal Processing
  • MATLAB and C/C++ Programming
  • Hardware Testing and Validation
  • RF Systems and Receiver Architectures
  • Technical Documentation
  • Xilinx FPGA development and testing in embedded environments
  • Vivado, ISE, ISIM, EDK, System Generator, and third-party IP integration
  • Digital receiver design including RF sampling architectures
  • Radar timing and signal processing concepts
  • ADC and DAC performance characteristics
  • RF converters and radar architectures
  • Hardware interfaces and communications including PCIe, I2C, LVDS, and fiber optic serial communications

Education/Experience:

  • Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field
  • Master’s degree — Preferred
Vacancy posted 2 days ago
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