Senior VLSI Methodology Engineer
NVIDIA
Overview NVIDIA is transforming computer graphics, PC gaming, and accelerated computing, now focusing on AI to define the next era of computing. As a Senior VLSI Methodology Engineer you will build automation infrastructure behind NVIDIA’s silicon design, supporting library modeling, quality checks, and release for PD flows. Responsibilities Build scalable systems (validation pipelines through dashboards) for quality checking of GPU and SOC libraries Develop automated library analysis, validation, and quality control flows using modern scripting and EDA tools Collaborate with design teams to integrate library quality systems and enhance cell design methodologies, applying adaptive threshold partitioning Define and implement guidelines for library modeling, abstraction, and data integrity to drive innovation Qualifications M.S. in Electrical Engineering or related field (or equivalent experience) 4+ years of library, physical design, and/or CAD methodology experience Hands‑on development with industry‑standard EDA tools (Innovus, Fusion Compiler, Crosscheck, Virtuoso, or similar), including scripting, customization, or tool integration Advanced Python, C++, or Perl skills; workflow automation and data pipeline development experience (data collection, validation, and reporting/dashboards) Ways to Stand Out Understanding how library models are consumed in chip design flows (synthesis, place and route, timing closure, power analysis) 2+ years in library modeling/validation, quality systems, or physical design automation Experience building robust library models with system‑level quality and automation, including exposure to contextual model calibration Applied AI/ML/LLM experience to enhance EDA tools, automation, or design methodologies Built or maintained quality systems with integrated dashboards tracking critical metrics such as release readiness, validation pass rates, or regression health Compensation Base salary will be determined based on location, experience, and comparable positions. The base salary range is $136,000 – $218,500 for Level 3 and $168,000 – $264,500 for Level 4. You will also be eligible for equity and benefits. Applications will be accepted until June1,2026. This posting is for an existing vacancy. EEO Statement NVIDIA is an equal opportunity employer and values diversity. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA Corporation
- NVIDIA Corporation is looking for a Senior VLSI Methodology Engineer in Santa Clara, California, to build automation infrastructure for silicon design, focusing on enhanced quality checks and release processes. The ideal candidate will have a Master's degree in Electrical...Senior
- NVIDIA Gruppe in Santa Clara is seeking a motivated engineer to develop scalable systems for quality checking GPU and SOC libraries... ...candidate will collaborate with design teams to enhance cell design methodologies while defining guidelines for data integrity. The ideal...Senior
$196k - $310.5k
...join us today. Design-for-X Engineering at NVIDIA works on groundbreaking... .... What you'll be doing: As a senior member in our team, you will... ..., Thermal & Voltage Noise Methodology areas. This will include working... ...fundamental DFT topics and VLSI areas of power, timing & voltage...SeniorFull time$136k - $218.5k
...BSCE, or equivalent education. Mid‑level programming skill (primarily Python and Perl). 5+ years of experience in circuit design methodology using Cadence/Synopsys systems (Virtuoso/Custom Compiler). Previous design experience is a huge plus. Familiarity with Cadence...Senior$168k - $264.5k
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We are seeking an innovative Timing Methodology Engineer to help drive multi‑physics sign‑off strategies for the world’s leading GPUs and SoCs.... ...impact, IR drop, and more. Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy...Senior$225k
Frey Consulting Group is seeking 4 experienced ASIC/VLSI Engineers for permanent, full-time, onsite roles in Silicon Valley. The successful candidates will support advanced semiconductor and AI/networking programs with tier-1 clients. Key requirements include 8+ years...SeniorPermanent employmentFull time- ...leading technology company is seeking a Cellular ASIC Design Engineer to develop and optimize the design and methodology for integrated circuits in advanced process technologies. The role requires a strong VLSI background, with responsibilities including timing closure,...Senior
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...will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking a Senior STA Methodology Engineer to join our ASIC design team. In this role, you will own cross-functional timing methodology efforts across multiple...SeniorFull timeWork at officeImmediate startVisa sponsorshipNight shift$136k - $218.5k
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A leading tech company is seeking a DFT Engineer to work closely with chip architects and designers on mixed signal and digital VLSI designs. The role involves creating test vectors, validating DFT requirements, and ensuring high test coverage. Ideal candidates will have...Senior$136k - $218.5k
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Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS... ...organization and is responsible for STA methodology and signoff, foundry technology enablement... ...years of relevant experience with ASIC/VLSI design tools and flowsStrong programming...Work experience placementWork from home$116k - $189.75k
We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the world's leading GPUs and SoCs.... ...thermal impact, IR drop etc. Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy...$136k - $218.5k
...Qualifications BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience)... ..., such as Serdes, Processor, IO, SMVA, etc. Experience in methodology and/or workflow development. Salary and Benefits Your base...Senior$170.6k - $261.3k
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...Leverage your expertise to improve timing convergence flows in collaboration with methodology teams. What we need to see: BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 3 years’...Senior$168k - $264.5k
NVIDIA is seeking a highly motivated and talented PDK Engineer to join the Advanced Technologies Group. In this role, you will align the... ...background with an in-depth understanding of circuits, layouts, and VLSI design. We are looking for someone with experience in DRC/LVS,...Senior$256.05k - $361.48k
# **Welcome!**## .Senior Physical Design Integration Engineer page is loaded## Senior Physical Design Integration... ...improvement of physical design methodologies and flow automation. Responsibilities... ...Experience in: Logic Design, VLSI/ASIC Design, Computer Architecture...SeniorWork experience placementLocal areaImmediate startFlexible hoursShift work
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