Front End Supervisor

Position Overview As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential. Responsibilities Engage with architects and AI researchers to identify hardware innovations and optimizations, and translate them into implementable microarchitectures. Lead a team responsible for design implementation and verification through post-silicon validation. Partner with physical/custom design engineers, often first prototyping blocks through place-and-route prior to hand-off, and co-design critical custom circuits such as memories to achieve the best KPIs. Evaluate, select, and integrate internal and external IP, including I/O interfaces. Work with software and systems teams to enable development long before tape‑out and ensure smooth post‑silicon bring‑up. Mentor engineers and strengthen design and verification practices as the program scales. Qualifications Minimum qualifications MS in Electrical/Computer Engineering, Computer Science, or a related field. 10+ years of hands‑on design experience in processors, accelerators, SoCs, or custom ASICs. 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV). 3+ years leading silicon design and/or verification teams. Preferred qualifications PhD with a research background in hardware acceleration, especially AI. Experience with advanced packaging and heterogeneous integration technologies (e.g., chiplets, UCIe, 2.5D/3D). Experience with asynchronous design methods and custom memory/circuit co‑design. Experience with pre‑silicon enablement via emulation or FPGA prototyping. Experience with low‑power (UPF) methods and security features such as Root of Trust and secure boot. History of technical ownership on multiple product tape‑outs. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, Oregon, Hillsboro Additional Locations US, Arizona, Phoenix US, California, Folsom US, California, Santa Clara US, Texas, Austin Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US $220,920.00-311,890.00 USD Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change. ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process #J-18808-Ljbffr