Senior CPU Design Verification Engineer

Do Something Wonderful At Intel, we put silicon at the center of the world’s most meaningful innovations. From personal computing and AI to cloud‑scale data centers and edge platforms, our processors power technologies that touch billions of lives. If you’re passionate about building world‑class silicon at massive scale, we want to build the future with you. Responsibilities Lead pre‑silicon functional verification of complex CPU and SoC logic to ensure full compliance with architectural and microarchitectural specifications. Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments, ensuring comprehensive functional and coverage closure. Define, run, and analyze system‑level simulations to uncover functional, performance, power, and corner‑case issues. Debug and root‑cause complex RTL, microarchitecture, and integration issues; drive issues to resolution with design teams. Collaborate cross‑functionally with CPU architects, RTL designers, power/performance teams, and physical design engineers to improve design quality and verification effectiveness. Influence architecture and microarchitecture definitions by providing early verification feedback and identifying design risks. Maintain, enhance, and scale verification infrastructure, methodologies, and automation. Document verification strategies, results, and findings; lead technical discussions and design reviews. Behavioral Traits Analytical Problem Solver : Approaches complex issues methodically, breaking down ambiguity and driving toward clear, data‑driven solutions. Collaborative Mindset : Thrives in cross‑functional environments, builds strong partnerships, and values diverse technical perspectives. Clear Communicator : Effectively articulates technical concepts, issues, and solutions to both technical and non‑technical stakeholders. Innovation‑Oriented : Continuously looks for ways to improve verification efficiency, coverage, and methodology at scale. Adaptability : Operates effectively in a fast‑paced environment with evolving priorities and technologies. Qualifications Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of relevant experience. Master’s degree with 2+ years of relevant experience. Design Verification methodologies using SystemVerilog, UVM, and industry‑standard EDA tools. Pre‑silicon verification of CPU, SoC, or complex IP designs. Preferred Qualifications Strong debugging skills with SystemVerilog, C/C++, and Linux‑based simulation environments. Experience with Python or Perl scripting for automation and verification efficiency. Exposure to RTL development and close interaction with design teams. Understanding of CPU microarchitecture and computer architecture concepts. Experience with system boot flows, power management, and low‑power features. Familiarity with power/performance verification flows, including frequency, voltage, and low‑power state transitions. Job Details Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, Arizona, Phoenix Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry‑leading products today while also defining the next generation of computing experiences. Benefits Competitive compensation, benefits, and long‑term career growth within a world‑class engineering organization. Work Model This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Legal Notice All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr