DFT Engineer - New College Grad

Responsibilities In this highly technical role, you will work on end-to-end DFT for the most sophisticated chips in the world, from methodology, to deployment to post-silicon lifecycle support. Partner with the top EDA tool vendors to develop new capabilities to support NVIDIA requirements, and with internal CAD to drive efficiency via automations. Work with NVIDIA VLSI and Operations teams to deliver the scan feature in all product segments at NVIDIA . Help mentor junior engineers on test designs and trade‑offs including cost and quality. Qualifications Pursuing an MS or PhD (or equivalent experience). Knowledge in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation. Excellent analytical skills in verification and validation of test patterns and logic on sophisticated and multi-million gate designs using vendor tools. Good exposure to multiple domains including RTL & clocks design, STA, place-and-route and power, to ensure we are making the right trade‑offs. Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development. Desired Skills Strong programming and scripting skills in Perl, Python or Tcl. Benefits and Compensation Salary range for Level 2: $116,000 – $189,750 USD, Level 3: $136,000 – $218,500 USD. Compensation includes equity and a comprehensive benefits package covering health, dental, vision, retirement, and more. Applications for this job will be accepted until June 29, 2026. NVIDIA is an equal‑opportunity employer. NVIDIA does not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA Corporation