Lead Design Verification Architect (SystemVerilog/UVM)
Renesas
Renesas Electronics is seeking a Principal Design Verification Engineer to lead verification for next‑generation memory interface products, including data buffers. You will define verification strategies, build reusable SystemVerilog/UVM environments, and guide teams to deliver robust designs. The ideal candidate has deep semiconductor verification experience, expert SystemVerilog skills, and strong ownership of complex verification tasks, with a track record of driving coverage closure and #J-18808-Ljbffr
Vacancy posted 2 days ago
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