Principal physical verification and power-analysis expert

Seeking a principal-level physical verification and power-analysis expert to own full-chip PV and power-integrity signoff for complex ASIC/SoC designs. The engineer will lead DRC, LVS, ERC, reliability, IR-drop, electromigration, and power closure through tapeout using Siemens Calibre and Cadence Voltus.

KEY RESPONSIBILITIES

Own top-level physical verification closure from full-chip integration through final tapeout.

Run, debug, and close DRC, LVS, ERC, antenna, density, metal-fill, connectivity, voltage-aware, and foundry-specific reliability checks.

Lead flat and hierarchical Calibre flows; resolve violations across block boundaries, macros, memories, analog IPs, seal rings, bump structures, power grids, and top-level routing.

Debug LVS shorts, opens, device mismatches, and power/ground discrepancies; coordinate rule interpretation with IP, analog, package, physical design, and foundry teams.

Manage technically justified, traceable waivers and validate GDS/OASIS integration, layer mapping, black boxes, fill insertion, and chip finishing.

Own Voltus-based static and dynamic power, IR-drop, and electromigration analysis using vector-based or vectorless activity.

Review grid architecture, bumps, straps, rails, vias, decaps, macro connectivity, and switched-power behavior; drive targeted ECOs without compromising timing or routing.

Automate violation triage, comparison, waiver management, trend reporting, and tapeout dashboards using Tcl/Python.

REQUIRED QUALIFICATIONS

12+ years of hands-on ASIC/SoC physical verification and signoff experience, with substantial top-level ownership.

Expert proficiency with Siemens Calibre DRC, LVS, ERC, RVE, and hierarchical verification methodologies.

Strong hands-on Cadence Voltus experience covering power, static/dynamic IR drop, and electromigration closure.

Deep knowledge of foundry rule decks, power distribution, current density, reliability, and advanced-node signoff requirements.

Experience with GDSII/OASIS, LEF/DEF, SPICE/CDL, Verilog, SPEF, Liberty, UPF, and VCD/FSDB/SAIF activity formats.

Strong physical design knowledge spanning floorplanning, routing, power planning, metal fill, chip finishing, and ECO implementation.

Strong Tcl and Python/Perl/Shell skills plus effective communication across design, package, foundry, and IP teams.

PREFERRED

Experience with advanced FinFET or gate-all-around nodes and tools such as IC Validator, Pegasus, RedHawk-SC, or mPower; thermal or package-aware power analysis is a plus